1. Field of the Invention
The present disclosure relates generally to packet network devices, and more particularly to methods and apparatus for retransmitting an epoch of data within such a device.
2. Description of Related Art
FIG. 1 shows one configuration for a distributed packet switching/routing platform 100, e.g., capable of operating as a packet switch in a packet network. Line cards LC1, LC2, LC3, and LC4 receive packet/frame data on ingress ports In1 and In2 and transmit packet/frame data on egress ports Eg3 and Eg4 (although typically each line card will have both ingress and egress ports, to simplify FIG. 1 only LC1 and LC2 are shown with ingress ports and only LC3 and LC4 are shown with egress ports). A switch fabric 70 connects to each line card to facilitate movement of packet data between the ingress and egress ports. As typically several line cards may receive ingress packets destined for the same egress line card and each line card may receive ingress packets destined for multiple egress line cards, a scheduler 60 determines a time-varying switch fabric configuration that attempts to treat all line cards fairly in distributing ingress packets to egress line cards.
Regarding line card LC1, several ingress-related blocks are depicted. PHY 20-1 receives electrical or optical signals at one or more ingress ports In1, and translates these signals to a frame bitstream/bitstreams. Ingress processing 30-1 receives the bitstream/bitstreams, detects frames/packets in the data, determines an egress line card that should receive each packet to move it toward its destination, and updates packet headers as necessary for each packet. Each packet is tagged with an internal tag that indicates the egress line card, packet priority, etc., and is then passed to ingress traffic manager (ITM) 40-1.
ITM 40-1 stores each tagged ingress packet in an ingress buffer/queue memory 50-1 until scheduler 60 grants a time slot for the packet to be transmitted across switch fabric 70. Within memory 50-1, the packets are sorted into queues based on destination line card, and possibly also based on other attributes such as a Quality of Service (QoS) attribute for the packet. ITM 40-1 communicates with scheduler 60 over scheduling bus 65 to report which queues have traffic waiting and how much traffic is waiting.
Within line card LC2, a PHY 20-2, ingress processing 30-2, an ITM 40-2, and an ingress buffer/queue memory 50-2 will be processing packets concurrently, in similar fashion as their counterparts on line card LC1, but for ingress ports In2.
Scheduler 60 divides time into epochs. Each epoch is a time slice during which switch fabric 70 will maintain a given configuration dictated by scheduler 60, and each epoch in this example is long enough to allow transmission of multiple 1500-byte packets (or even more smaller packets) from an ITM. The switch fabric configuration for an upcoming epoch is communicated to each ingress traffic manager. Assume, e.g., that for the upcoming epoch, ingress traffic manager 40-1 will be allowed to transmit packets to an egress traffic manager 80-3 on line card LC3. In this case, ingress traffic manager 40-1 will prepare to send packets from one or more LC3-bound queues to switch fabric 70 on a port pipe 55-1 when the epoch actually begins. Epoch traffic manager 40-2 will concurrently prepare to send packets during the upcoming epoch to a different line card (e.g., LC4) per the configuration granted by scheduler 60.
Switch fabric 70 switches packets from its ingress port pipes (port pipes 55-1 and 55-2 are shown) to its egress port pipes (port pipes 75-3 and 75-4 are shown). For each epoch, scheduler 60 instructs switch fabric 70 as to which egress port pipe(s), if any, should be connected to each ingress port pipe. Switch fabric 70 sets the necessary switching configuration to support data transfer between the ingress and egress port pipes during the epoch.
Line cards LC3 and LC4 are shown with analogous elements to the ingress elements of line cards LC1 and LC2. Line card LC3 contains an egress traffic manager (ETM) 80-3 that receives epoch data from port pipe 75-3 and stores the epoch data in an egress buffer/queue memory 90-3. ETM 80-3 sends packets from memory 90-3 to egress processing 95-3, which readies the packets/frames for transmission and forwards them to the appropriate channel on PHY 20-3. PHY 20-3 converts the packets/frames to the optical or electrical format for the transmission medium used on egress ports Eg3. Line card LC4 performs analogous functions with an ETM 80-4, an egress buffer/queue memory 90-4, egress processing 95-4, and PHY 20-4, for egress port pipe 75-4 and egress ports Eg4.
Each traffic manager interfaces with its port pipe through a port pipe FIFO (First-In First-Out), which is a circular buffer capable of holding about 1.2 epochs of data. ITM 40-1 fills a port pipe FIFO 45-1 with packet data stored in an appropriate queue in memory 50-1, based on a first pointer into the circular buffer. Concurrently, a second pointer synchronized to the start of each epoch empties data for the current epoch from the FIFO to port pipe 55-1. ETM 80-3 empties a port pipe FIFO 85-3 to its buffer memory 90-3 based on a first pointer into that circular buffer. Concurrently, a second pointer synchronized to the start of each epoch fills the FIFO with epoch data for the current epoch from port pipe 75-3.
Several timed events determine what queue is used to fill an ingress port pipe FIFO, and when each FIFO will be filled and emptied. FIG. 2 presents a timing example that further illustrates the epoch timing for transmission of packets between an ingress traffic manager and an egress traffic manager. Each epoch occupies a fixed time segment of period TE. Four full epochs 1-4 and parts of epochs 0 and 5 are illustrated.
The first event shown in FIG. 2 occurs during epoch 0. Towards the end of epoch 0, scheduler 60 transmits a GRANT to ITMs 40-1 and 40-2. The GRANT instructs each ITM as to which egress line card it will be paired with for an upcoming epoch. The GRANT is received just over an epoch prior to when data corresponding to the GRANT will begin emptying from the ingress port pipe FIFOs 45-1 and 45-2. For instance, the GRANT B received near the end of epoch 0 in FIG. 2 pertains to GRANT B data that will be transmitted through the switch fabric during epoch 2.
After receiving GRANT B, ITM 40-1 begins filling port pipe FIFO 45-1 with data B1 for GRANT B (although the figures show the fill operation beginning at the next start-of-epoch, in practice the fill operation can begin when the grant is received). In FIG. 2, the contents of FIFO 45-1 are represented as a buffer map as a function of time, with the top of the FIFO 45-1 time history representing a physical buffer location at one “end” of the buffer and the bottom of the FIFO 45-1 time history representing a physical buffer location at the other “end” of the buffer. The FIFO is filled starting from a buffer position just after the end of the FIFO data A1 for a preceding GRANT A, with the slanted left edge of region B1 representing the filling operation. Note that as data B1 for GRANT B begins to fill FIFO 45-1, a Start Of Epoch (SOE) signal is received for epoch 1, signaling that it is time to begin emptying data A1 for GRANT A from FIFO 45-1. As GRANT A data is read out of FIFO 45-1, GRANT B data overwrites most of the space just occupied by GRANT A data. The GRANT A data has, however, been placed on port pipe 55-1 for transmission to LC3, and is no longer needed by ITM 40-1.
During epochs 1 and 3, switch fabric 70 is passing data from ingress port pipe 55-1 to egress port pipe 75-3, and from ingress port pipe 55-2 to egress port pipe 75-4. During epochs 2 and 4, this ingress-to-egress pairing is reversed The same data appears on the paired ingress and egress port pipes during an epoch, with the egress port pipe data slightly delayed due to switch fabric handling delay. GRANT A data appears on the port pipes during epoch 1, GRANT B data appears on the port pipes during epoch 2, and so on.
Egress port pipe FIFOs 85-3 and 85-4 operate similar to ingress port pipes 45-1 and 45-2, except they are filled from their port pipe and emptied by their ETM to the egress buffer memory. Because of the alternating switch fabric configuration used in this example, each egress port pipe receives data from one ingress card during even epochs and from the other ingress card during odd epochs.
Each epoch of data is finally completely resident in its destination egress buffer about three epochs after the grant for that epoch of data. It can be seen that this scheduler grant sequence could be modified should one ingress card receive data weighted more towards one egress card than the other. In a system with more than two ingress port pipes and two egress port pipes, scheduling will result in many more permutations for grants as a function of time, but the preceding example illustrates the essential functionality that is scaled for a larger number of port pipes.